IP BASED SOC DESIGN'2003 will be the 12th edition of the IFIP workshop on hot topics in the design world, focusing for the past three years on IP based SoC design and qualification. WORKING CONFERENCE Among 90 submissions the best technical contributions have been selected to bring together a high level working conference unique on hot topics such as "ASIC Platform","SystemC for IP Modeling" "Impact of Nanometer Technology", "IP/SoC Verification", etc... Please click here to read the program KEYNOTE TALKS Major players will deliver keynote talks on hot topics and you will be delighted to listen to : Santanu Dutta, IC Design manager at Philips Semiconductors (USA) talking about "Recent Trends in Multi-Million-Gate SOC Designs" Ted Vucurevich , CTO of Cadence (USA) discussing "Design platform for IP based SOC design" Raul Camposano, CTO of Synopsys (USA) sharing his experiences in "The IP Provider Game: Size and Diversity Do Matter" Jim Tully, Chief Analyst from Gartner / Dataquest (UK) presenting the studies on the "Dataquest IP business analysis" HOT PANELS Hot Panels will be part of an attractive program and every participant will be invited to share his views with the audience: "Configurable Processors and Reconfigurable Logic: Flexible Architectures for SOCs" organized by Steve Leibson, Tensilica (USA) with the participation of IBM Research Lab (Switzerland), MIPS Technologies , DAFCA (Design Automation for Flexible Chip Architectures) (USA), Laboratoire LIRMM (France), Analyst and editors from Gilder Technology, MicroDesign Resource, Gartner Research (UK) "IP qualification : the user camp versus the tool and IP vendor camp" organized by Philippe Magarshack, ST Microelectronics (France) with the participation of Alcatel (France), Philips (The Netherlands), ST Microelectronics (France) in the user camp and ARM (UK), Mentor Graphics (USA), Synopsys (USA), Verisity (USA) in the tool and IP provider camp "Asic platform: the key for successful IP based SOC design Core based or interconnect based or technology structured ? " organized by Tim Daniels, LSI Logic (UK) & Joe Hanson, Altera (USA) with the participation of LSI Logic (UK), Altera (USA), Sonics (USA), the Spirit consortium (The Netherlands), etc... "SystemC in Harmony, not in conflict with RTL" organized by G. Arnout, CoWare chairman and OSCI president with the participation of M. Burton from ARM, F. Ghenassia from STMicroelectronics, J. Aynsley from Doulos, etc... "IP business models" organized by P.Dworsky, Synopsys (USA) with the participation of ARM (UK), ST Microelectronics (France), Gartner / Dataquest (UK), etc.. IP/SOC 2003 BEST PRIZES The contest for delivering the best IP/SOC design 2003 will be organised by Prof. Kunihiro Asada from the Tokyo university. This year 4 candidates preselected by the LSI IP Design Award in Japan will be in competition with 4 additional candidates for winning this prestigious award sponsored by ST Microelectronics EXHIBITION In addition the "IP based SOC Design Workshop" has an exhibition attached, giving you the opportunity to see the reality of a SOC connected world. The joint exciting dedicated exhibition will allow you to meet the most advanced suppliers and take the chance to see the last products of the best vendors including Aptix, Artisan Components, Barco Silex, Coware, Design And Reuse, GeTeDes, Jennic Ltd., Mentor Graphics, Novas Software, OCPIP, Prosilog, Silicon and Software Systems , Soisic, SuperH, Synchronicity , Synopsys, Target Compiler, VCX Software Ltd., Verisity , Virage Logic and so on. You can still book your space. SEMINAR A seminar takes place November 12th evening and has as objectives to report to the IP/SOC community and especially to D&R partners the role and achievement of D&R Entrance is free but registration is required IMPORTANT DATES Final Version of the manuscript October 20th, 2003 Workshop November 13-14th, 2003 LOCATION Espace Congres du World Trade Center 5 place Robert Schuman 38 000 Grenoble FRANCE LAST MINUTE The foils of the presentations of the previous edition are available online, see : http://www.us.design-reuse.com/ipbasedsocdesign -------------------------------------------------------------------------------- AROUND WWW.DESIGN-REUSE.COM SPONSOR MESSAGE True Circuits, Inc. offers a complete family of innovative, standardized and silicon proven PLL hard macros with LockNow! TM Technology for very fast locking with minimal frequency overshoot. All PLLs are available in a range of frequencies, multiplication factors and functions in TSMC and UMC processes from 0.25um to 0.09um. Call (650) 691-2500 or visit http://www.truecircuits.com/dr2. SOC NEWS ALERTS Receive free news updates related to the SoC field on your desktop on a regular basis, go to : http://www.us.design-reuse.com/users/change_settings.php D&R SOFTWARE IP CATALOG A catalog of Hardware dependent Software (HdS) ranging from embedded OS to Communication Stacks and Application Software go to : http://www.us.design-reuse.com/hds MISSED IP BASED DESIGN 2002 ???? The presentations are available online, go to : http://www.us.design-reuse.com/ipbasedsocdesign -------------------------------------------------------------------------------- CHANGE OF ADDRESS/UNSUBSCRIBE You are subscribed as dolinsky@gsu.by. If you wish to unsubscribe or if you wish to receive this letter in "Plain Text" format , you can do it there If you need to change the e-mail address at which you receive this newsletter, you can do it there -------------------------------------------------------------------------------- Corporate Headquarters: Design And Reuse World Trade Center 5 place Robert Schuman 38025 Grenoble Cedex FRANCE Tel: +33 476 70 64 87 Fax: +33 476 70 64 53 info@design-reuse.com US office: Design And Reuse 5600 Mowry School Road Suite 180 Newark, CA 94560 USA Tel: +1 510 656 1445 Fax: +1 510 656 0995 info@design-reuse.com